MC74LCX245 Low-Voltage CMOS Octal Transceiver

With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting)

The MC74LCX245 is a high performance, non−inverting octal transceiver operating from a 2.0 to 5.5 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5 V allows MC74LCX245 inputs to be safely driven from 5 V devices if VCC is less than 5.0 V. The MC74LCX245 is suitable for memory address driving and all TTL level bus oriented transceiver applications.

Current drive capability is 24 mA at both A and B ports. The Transmit/Receive (T/R) input determines the direction of data flow through the bi−directional transceiver. Transmit (active−HIGH) enables data from A ports to B ports; Receive (active−LOW) enables data from B to A ports. The Output Enable input, when HIGH, disables both A and B ports by placing them in a HIGH Z condition.

Features

• Designed for 2.0 to 5.5 V VCC Operation

• 5 V Tolerant − Interface Capability With 5 V TTL Logic

• Supports Live Insertion and Withdrawal

• I_OFF Specification Guarantees High Impedance When VCC = 0 V

• LVTTL Compatible

• LVCMOS Compatible

• 24 mA Balanced Output Sink and Source Capability

• Near Zero Static Supply Current in All Three Logic States (10 A)

Substantially Reduces System Power Requirements

• Latchup Performance Exceeds 500 mA

• ESD Performance: Human Body Model >2000 V

Machine Model >200 V

• NLV Prefix for Automotive and Other Applications Requiring Unique Site and

Control Change Requirements; AEC−Q100 Qualified and PPAP Capable

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant

MAXIMUM RATINGS

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. I_O absolute maximum rating must be observed.

MARKING DIAGRAMS

Pinout (Top View)

Logic Diagram

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